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exar corporation 48720 kato road, fremont ca, 94538 ? (510) 668-7000 ? fax (510) 668-7017 ? www.exar.com xra1202/1202p 8-bit i2c/smbus gpio expander with reset april 2013 rev. 1.0.1 general description the xra1202/1202p is an 8-bit gpio expander with an i 2 c/smbus interface. after power-up, the xra1202 has internal 100k ohm pull-up resistors on each i/o pin that can be individually enabled. the xra1202p has the internal pull-up resistors enabled upon power-up in case it is necessary for the input s to be in a known state. in addition, the gpios on the xra1202/1202p can individually be controlled and configured. as outp uts, the gpios can be outputs that are high, low or in three-state mode. the three-state mode feature is useful for applications where the power is removed from the remote devices, but they may still be connected to the gpio expander. as inputs, the internal pull-up resistors can be enabled or disabled and the input polarity can be inverted. the interrupt can be programmed for different behaviors. the interrupts can be programmed to generate an interrupt on the rising edge, falling edge or on both edges. the interrupt can be cleared if the input changes back to its ori ginal state or by reading the current state of the inputs . the xra1202/1202p are enhanced versions of the pca9538. the xra1202 is pin and software compatible with the pca9538 (note: software registers are compatible to the pca9538, but the i 2 c slave address is different). the xra1202 is available in 16-pin qfn and 16-pin tssop packages. the xra1202p is available in the 16-pin qfn package. features 1.65v to 3.6v operating voltage 8 general purpose i/os (gpios) 5v tolerant inputs maximum stand-by current of 1ua at +1.8v i 2 c/smbus bus interface n i 2 c clock frequency up to 400khz n noise filter on sda and scl inputs n up to 16 i 2 c slave addresses individually programmable inputs n internal pull-up resistors n polarity inversion n individual interrupt enable n rising edge and/or falling edge interrupt n input filter individually programmable outputs n output level control n output three-state control open-drain active low interrupt output active-low reset input pin and software compatible with pca9538 3kv hbm esd protection per jesd22-a114f 200ma latch-up performance per jesd78b applications personal digital assistants (pda) cellular phones/data devices battery-operated devices global positioning system (gps) bluetooth
xra1202/1202p 2 8-bit i2c/smbus gpio expander with reset rev. 1.0.1 n ote : tr = tape and reel, f = green / rohs f igure 1. xra1202/1202p b lock d iagram ordering information p art n umber p ackage n umber o f gpio s o perating t emperature r ange d evice s tatus xra1202il16-f qfn-16 8 -40c to +85c active xra1202il16tr-f qfn-16 8 -40c to +85c active xra1202pil16-f qfn-16 8 -40c to +85c active XRA1202PIL16TR-F qfn-16 8 -40c to +85c active xra1202ig16-f tssop-16 8 -40c to +85c active xra1202ig16tr-f tssop-16 8 -40c to +85c active f igure 2. p in o ut a ssignments i 2 c/ smbus interface a1 a0 scl sda gpio control registers reset# irq# p0 gpios p1 p2 p3 p4 p5 p6 p7 vcc (1.65v C 3.6v) gnd xra1202 16-pin tssop 35 47 6 8 1 2 a0 a1 reset# p0 p1 p2 p3 gnd 9 10 11 12 13 14 15 16 vcc sda scl irq# p7 p6 p5 p4 xra1202/ xra1202p 16-pin qfn p1 p2 p0 reset# gnd p3 p4 p5 a0 a1 vcc sda p7 p6 irq# scl 16 15 14 13 5 6 7 8 2 13 4 11 12 10 9
xra1202/1202p 3 rev. 1.0.1 8-bit i2c/smbus gpio expander with reset pin descriptions pin type: i=input, o=output, i/o= input/output, od =output open drain. pin description n ame qfn-16 p in # tssop-16 p in # t ype d escription i 2 c interface sda 13 15 i/o i 2 c-bus data input/output (open-drain). scl 12 14 i i 2 c-bus serial input clock. irq# 11 13 od interrupt output (open-drain, active low). a0 a1 15 16 12 ii these pins select the i 2 c slave address. see table 1 . reset# 1 3 i reset (active low) - a longer than 40 ns low pulse on this pin will reset the internal registers and all gpios will be configured as inputs. gpios p0 p1 p2 p3 p4 p5 p6 p7 23 4 5 7 8 9 10 45 6 7 9 10 11 12 i/o i/o i/o i/o i/o i/o i/o i/o general purpose i/os p0-p7. all gpios are configur ed as inputs upon power- up or after a reset. after power-up or reset, the internal pull-up resistors are enabled for the xra1202p. after power-up or reset, the internal pull-up resis- tors are disabled for the xra1202. ancillary signals vcc 14 16 pwr 1.65v to 3.6v vcc supply voltage. gnd 6 8 pwr power supply common, ground. gnd center pad - pwr the exposed pad at the bottom surface of the packag e is designed for thermal performance. use of a center pad on the pcb is stro ngly recommended for ther- mal conductivity as well as to provide mechanical s tability of the package on the pcb. the center pad is recommended to be solder mas ked defined with open- ing size less than or equal to the exposed thermal pad on the package bottom to prevent solder bridging to the outer leads of the d evice. thermal vias must be connected to gnd plane as the thermal pad of packag e is at gnd potential.
xra1202/1202p 4 8-bit i2c/smbus gpio expander with reset rev. 1.0.1 1.0 functional descriptions 1.1 i 2 c-bus interface the i 2 c-bus interface is compliant with the standard-mode and fast-mode i 2 c-bus specifications. the i 2 c-bus interface consists of two lines: serial data (sda) and serial clock (scl). in the standard-mode, the serial clock and serial data can go up to 100 kbps and in the fa st-mode, the serial clock and serial data can go up to 400 kbps. the first byte sent by an i 2 c-bus master contains a start bit (sda transition f rom high to low when scl is high), 7-bit slave address and whether it is a read or write transaction. the next byte is the sub-add ress that contains the address of the register to access. the xra120x responds to each write with an acknowledge (sda driven low by xra1202/1202p for one clock cycl e when scl is high). the last byte sent by an i 2 c- bus master contains a stop bit (sda transition from low to high when scl is high). see figures 3 - 5 below. for complete details, see the i 2 c-bus specifications. f igure 3. i 2 c s tart and s top c onditions f igure 4. m aster w rites t o s lave f igure 5. m aster r eads f rom s lave sda scl s p start condition stop condition s w a a a p s l a v e a d d r e s s c o m m a n d b y t e d a t a b y t e w h ite b lo c k : h o s t to x r a 1 2 0 x g re y b lo c k : x r a 1 2 0 x to h o s t s w a a r slave address command byte white block: host to xra120x grey block: xra120x to host a s slave address ndata a na p last data
xra1202/1202p 5 rev. 1.0.1 8-bit i2c/smbus gpio expander with reset 1.1.1 i 2 c-bus addressing there could be many devices on the i 2 c-bus. to distinguish itself from the other device s on the i 2 c-bus, the xra1202/1202p has up to 16 i 2 c slave addresses using the a1-a0 address lines. table 1 below shows the different addresses that can be selected. t able 1: i 2 c a ddress m ap a1 a0 i 2 c a ddress scl gnd 0x20 (0010 000x) scl vcc 0x22 (0010 001x) sda gnd 0x24 (0010 010x) sda vcc 0x26 (0010 011x) scl scl 0x30 (0011 000x) scl sda 0x32 (0011 001x) sda scl 0x34 (0011 010x) sda sda 0x36 (0011 011x) gnd gnd 0x40 (0100 000x) gnd vcc 0x42 (0100 001x) vcc gnd 0x44 (0100 010x) vcc vcc 0x46 (0100 011x) gnd scl 0x50 (0101 000x) gnd sda 0x52 (0101 001x) vcc scl 0x54 (0101 010x) vcc sda 0x56 (0101 011x)
xra1202/1202p 6 8-bit i2c/smbus gpio expander with reset rev. 1.0.1 1.1.2 i 2 c read and write a read or write transaction is determined by bit-0 of the slave address. if bit-0 is 0, then it is a write transaction. if bit-0 is 1, then it is a read tr ansaction. 1.1.3 i 2 c command byte an i 2 c command byte is sent by the i 2 c master following the slave address. the command byte indicates the address offset of the register that will be accesse d. table 2 below lists the command bytes for each register. t able 2: i 2 c c ommand b yte (r egister a ddress ) c ommand b yte r egister n ame d escription r ead /w rite d efault v alues 0x00 gsr - gpio state read-only 0xxx 0x01 ocr - output control read/write 0xff 0x02 pir - input polarity inversion read/write 0x00 0x03 gcr - gpio configuration read/write 0xff 0x04 pur - input internal pull-up resistor enable/di sable read/write 0x00 (xra1202) 0xff (xra1202p) 0x05 ier - input interrupt enable read/write 0x00 0x06 tscr - output three-state control read/write 0x00 0x07 isr - input interrupt status read 0x00 0x08 reir - input rising edge interrupt enable read/w rite 0x00 0x09 feir - input falling edge interrupt enable read/ write 0x00 0x0a ifr - input filter enable/disable read/write 0xff
xra1202/1202p 7 rev. 1.0.1 8-bit i2c/smbus gpio expander with reset 1.2 interrupts the table below summarizes the interrupt behavior o f the different register settings for the xra1202/1 202p. t able 3: i nterrupt g eneration and c learing gcr b it ier b it reir b it feir b it ifr b it i nterrupt g enerated b y : i nterrupt c leared b y : 1 0 x x x no interrupts enabled (default) n/a 1 1 0 0 0 a rising or falling edge on the input reading the g sr register or if the input changes back to its previous state (state of input during last read to gsr) 1 a rising or falling edge on the input and remains in the new state for more than 1075ns 1 1 1 0 0 a rising edge on the input reading the gsr register 1 a rising edge on the input and remains high for more than 1075ns 1 1 0 1 0 a falling edge on the input reading the gsr registe r 1 a falling edge on the input and remains low for more than 1075ns 1 1 1 1 0 a rising or falling edge on the input reading the g sr register 1 a rising or falling edge on the input and remains in the new state for more than 1075ns 0 x x x x no interrupts in output mode n/a
xra1202/1202p 8 8-bit i2c/smbus gpio expander with reset rev. 1.0.1 2.0 register description 2.1 gpio state register (gsr) - read-only the status of p7 - p0 can be read via this register . a read will show the current state of these pins (or the inverted state of these pins if enabled via the pir register). reading this register will clear an in put interrupt (see table 3 for complete details). reading this register will also return the last value written to the ocr register for any pins that are configured as output s (ie. this is not the same as the state of the act ual output pin since the output pin can be in three-state mode). a write to this register has no effect. the msb of this register corresponds with p7 and the lsb of this register co rresponds with p0. 2.2 output control register (ocr) - read/write when p7 - p0 are defined as outputs, they can be co ntrolled by writing to this register. reading this register will return the last value written to it, however, this value may not be the actual state of the outpu t pin since these pins can be in three-state mode. the msb of this register corresponds with p7 and the lsb of th is register corresponds with p0. 2.3 input polarity inversion register (pir) - read/w rite when p7 - p0 are defined as inputs, this register i nverts the polarity of the input value read from th e input port register. if the corresponding bit in this registe r is set to 1, the value of this bit in the gsr r egister will be the inverted value of the input pin. if the correspond ing bit in this register is set to 0, the value o f this bit in the gsr register will be the actual value of the input pin. the msb of this register corresponds with p7 and the lsb of this register corresponds with p0. 2.4 gpio configuration register (gcr) - read/write this register configures the gpios as inputs or out puts. after power-up and reset, the gpios are inpu ts. setting these bits to 0 will enable the gpios as outputs. setting these bits to 1 will enable the gpios as inputs. the msb of this register corresponds with p7 and the lsb of this register corresponds with p0 . 2.5 input internal pull-up enable/disable register ( pur) - read/write this register enables/disables the internal pull-up resistors for an input. after power-up and reset, the internal pull-up resistors are disabled for the xra1202. wr iting a 1 to these bits will enable the internal pull-up resistors. after power-up and reset, the internal pull-up resistors are enabled for the xra1202p. wr iting a 0 to these bits will disable the internal pull-up res istors. the msb of this register corresponds with p7 and the lsb of this register corresponds with p0. 2.6 input interrupt enable register (ier) - read/wri te this register enables/disables the interrupts for a n input. after power-up and reset, the interrupts are disabled. writing a 1 to these bits will enable the interru pt for the corresponding input pins. see table 3 for complete details of the interrupt behavior for various regis ter settings. no interrupts are generated for outpu ts when gcr bit is 0. the msb of this register corresponds with p7 and the lsb of this register corresponds with p 0. 2.7 output three-state control register (tscr) - rea d/write this register can enable/disable the three-state mo de of an output. writing a 1 to these bits will enable the three-state mode for the corresponding output pins. the msb of this register corresponds with p7 and the lsb of this register corresponds with p0. 2.8 input interrupt status register (isr) - read-onl y this register reports the input pins that have gene rated an interrupt. see table 3 for complete details of the interrupt behavior for various register settings. the msb of this register corresponds with p7 and th e lsb of this register corresponds with p0.
xra1202/1202p 9 rev. 1.0.1 8-bit i2c/smbus gpio expander with reset 2.9 input rising edge interrupt enable register (rei r) - read/write writing a 1 to these bits will enable the corresp onding input to generate an interrupt on the rising edge. see table 3 for complete details of the interrupt behavior for various register settings. the msb of this regist er corresponds with p7 and the lsb of this register co rresponds with p0. 2.10 input falling edge interrupt enable register (f eir) - read/write writing a 1 to these bits will enable the corresp onding input to generate an interrupt on the fallin g edge. writing a 1 to these bits will make that input ge nerate an interrupt on the rising edge only. see table 3 for complete details of the interrupt behavior for vari ous register settings. the msb of this register co rresponds with p7 and the lsb of this register corresponds wi th p0. 2.11 input filter enable register (ifr) - read/write by default, the input filters are enabled (ifr = 0x ff). when the input filters are enabled, any pulse that is greater than 1075ns will generate an interrupt (if enabled). pulses that are less than 225ns will be filtered and will not generate an interrupt. pulses in between this range may or may not generate an interrupt. w riting a 0 to these bits will disable the input filter for the corresponding inputs. with the input filters disa bled, any change on the inputs will generate an interrupt (if enable d). see table 3 for complete details of the interrupt behavior for various register settings. the msb of this reg ister corresponds with p7 and the lsb of this regis ter corresponds with p0.
xra1202/1202p 10 8-bit i2c/smbus gpio expander with reset rev. 1.0.1 absolute maximum ratings power supply voltage 3.6 volts supply current 160 ma ground current 200 ma external current limit of each gpio 25 ma total current limit for gpio[7:0] 100 ma total supply current sourced by all gpios 160 ma operating temperature -40 o to +85 o c storage temperature -65 o to +150 o c power dissipation 200 mw typical package thermal resistance data (margin of error: 15%) thermal resistance (16-qfn) theta-ja = 40 o c/w, theta-jc = 26 o c/w thermal resistance (16-tssop) theta-ja = 105 o c/w, theta-jc = 20 o c/w
xra1202/1202p 11 rev. 1.0.1 8-bit i2c/smbus gpio expander with reset n otes : 1. for i 2 c input signals (sda, scl); 2. for gpios, a0, a1 and a2 signals; 3. for i 2 c output signal sda; 4. for gpios; 5. for irq# signal; electrical characteristics dc electrical characteristics u nless otherwise noted : ta = -40 o to +85 o c, v cc is 1.65v to 3.6v s ymbol p arameter l imits 1.8v 10% m in m ax l imits 2.5v 10% m in m ax l imits 3.3v 10% m in m ax u nits c onditions v il input low voltage -0.3 0.3vcc -0.3 0.3vcc -0.3 0.3vcc v not e 1 v il input low voltage -0.3 0.2 -0.3 0.5 -0.3 0.8 v note 2 v ih input high voltage 1.3 vcc 1.8 vcc 2.3 vcc v note 1 v ih input high voltage 1.4 5.5 1.8 5.5 2.0 5.5 v note 2 v ol output low voltage 0.4 0.4 0.4 v vv i ol = 3 ma i ol = 3 ma i ol = 3 ma note 3 v ol output low voltage 0.5 0.5 0.5 v i ol = 8 ma note 4 v ol output low voltage 0.4 0.4 0.4 v vv i ol = 6 ma i ol = 4 ma i ol = 1.5 ma note 5 v oh output high voltage 1.2 1.8 2.6 v vv i oh = -8 ma i oh = -8 ma i oh = -8 ma note 4 i il input low leakage current 10 10 10 ua i ih input high leakage current 10 10 10 ua i cc power supply current 50 100 200 ua test 1 i cc power supply current 150 250 500 ua test 2 i ccs standby current 1 2 5 ua test 3 c in input pin capacitance 5 5 5 pf r gpio gpio pull-up resistance 60 140 60 140 60 140 k w 100k w 40% r reset# reset# pull-up resistance 35 85 35 85 35 85 k w 60k w 40%
xra1202/1202p 12 8-bit i2c/smbus gpio expander with reset rev. 1.0.1 test 1: scl frequency is 400 khz with internal pull -ups disabled. all gpios are configured as inputs. all inputs are steady at vcc or gnd. outputs are floating or in the tri-s tate mode. test 2: scl frequency is 400 khz with internal pull -ups enabled. all gpios are configured as inputs. a ll inputs are steady at vcc or gnd. outputs are floating or in the tri-s tate mode. test 3: all inputs are steady at vcc or gnd to mini mize standby current. if internal pull-up is enable d, input voltage level should be the same as vcc. all gpios are configured as inputs. scl and sda are at vcc. outputs are lef t floating or in tri-state mode. ac electrical characteristics unless otherwise noted: ta=-40 o to +85 o c, vcc=1.65v - 3.6v s ymbol p arameter s tandard m ode i 2 c-b us m in m ax f ast m ode i 2 c-b us m in m ax u nit f scl operating frequency 0 100 0 400 khz t buf bus free time between stop and start 4.7 1.3 m s t hd;sta start condition hold time 4.0 0.6 m s t su;sta start condition setup time 4.7 0.6 m s t hd;dat data hold time 0 0 ns t vd;ack data valid acknowledge 0.6 0.6 m s t vd;dat scl low to data out valid 0.6 0.6 ns t su;dat data setup time 250 150 ns t low clock low period 4.7 1.3 m s t high clock high period 4.0 0.6 m s t f clock/data fall time 300 300 ns t r clock/data rise time 1000 300 ns t sp pulse width of spikes tolerance 50 50 ns t d1 i 2 c-bus gpio output valid 0.2 0.2 m s t d4 i 2 c input pin interrupt valid 4 4 m s t d5 i 2 c input pin interrupt clear 4 4 m s t d15 scl delay after reset 3 3 m s
xra1202/1202p 13 rev. 1.0.1 8-bit i2c/smbus gpio expander with reset f igure 6. i 2 c-b us t iming d iagram f igure 7. w rite t o o utput f igure 8. gpio p in i nterrupt start condition (s) bit 7 msb (a7) bit 6 (a6) protocol t buf t r t su;sta t low t high 1/f scl t f scl t hd;sta t su;dat t hd;dat sda bit 0 lsb (r/w) acknowledge (a) stop condition (p) t vd;dat t sp t vd;ack t su;sto slave address w a command byte a data a sda gpion t d1 s la v e a d d r e s s w a c o m m a n d b y t e a d a t a a s d a in t # t d 5 r a s l a v e a d d r e s s s p x t d 4 p a c k from slave a c k from slave a c k from m aster
xra1202/1202p 14 8-bit i2c/smbus gpio expander with reset rev. 1.0.1 package dimensions (16 pin qfn - 3 x 3 x 0.9 mm, 0.50 pitch ) note: the control dimension is in millimeter. inches millimeters symbol min max min max a 0.031 0.039 0.80 1.00 a1 0.000 0.002 0.00 0.05 a3 0.000 0.008 0.00 0.20 d 0.118 bsc 3.00 bsc d2 0.063 0.071 1.60 1.80 b 0.010 0.014 0.25 0.35 e 0.020 bsc 0.50 bsc l 0.012 0.020 0.30 0.50 q 0 14 o 0 14 o k 0.008 - 0.20 - note: the actual center pad is metallic and the size (d2) is device-dependent with a typical tolerance of 0.3mm q
xra1202/1202p 15 rev. 1.0.1 8-bit i2c/smbus gpio expander with reset package dimensions (16 pin tssop - 4.4 mm ) note: the control dimension is in millimeter. inches millimeters symbol min max min max a 0.031 0.047 0.80 1.20 a1 0.002 0.006 0.05 0.15 a2 0.031 0.037 0.80 0.95 b 0.007 0.012 0.19 0.30 c 0.004 0.008 0.09 0.2 d 0.193 0.201 4.90 5.10 e 0.240 0.264 6.30 6.60 e1 0.169 0.177 4.30 4.50 e 0.0256 bsc 0.65 bsc l 0.018 0.030 0.45 0.75 a 0 8 0 8
16 notice exar corporation reserves the right to make changes to the products contained in this publication in o rder to improve design, performance or reliability. exar co rporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representa tion that the circuits are free of patent infringement. chart s and schedules contained here in are only for illu stration purposes and may vary depending upon a users speci fic application. while the information in this publ ication has been carefully checked; no responsibility, howe ver, is assumed for inaccuracies. exar corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonabl y be expected to cause failure of the life support system or to significantly affect its safety or effectiveness . products are not authorized for use in such appli cations unless exar corporation receives, in writing, assurances t o its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks ; (c) potential liability of exar corporation is ad equately protected under the circumstances. copyright 2013 exar corporation datasheet april 2013. send your uart technical inquiry with technical det ails to hotline: uarttechsupport@exar.com . reproduction, in part or whole, without the prior w ritten consent of exar corporation is prohibited. xra1202/1202p 8-bit i2c/smbus gpio expander with reset rev. 1.0.1 revision history d ate r evision d escription september 2011 1.0.0 initial released datasheet for x ra1202. april 2013 1.0.1 added new xra1202p part numbers: xra 1202pil16-f and XRA1202PIL16TR-F.

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